1. Field
The present disclosure relates generally to processing systems, and more specifically, to systems and techniques for performing auxiliary writes over the address channel of a bus.
2. Background
At the heart of most modern processing systems is an interconnect referred to as a bus. The bus moves information between various processing entities in the system. Today, most bus architectures are fairly standardized. These standardized bus architectures typically have independent and separate read, write and address channels.
This type of bus architecture is often found in processing systems with one or more general purpose processors supported by memory. In these systems, the memory provides a storage medium that holds the programs and data needed by the processors to perform their functions. A processor may read or write to the memory by placing an address on the address channel and sending the appropriate read/write control signal. Depending on the state of the read/write control, the processor either writes to the memory over the write channel or reads from the memory over the read channel. In these types of processing systems, as well as many others, it is desirable to reduce the write latency and increase the write bandwidth.